1. Field of the Invention
The present invention generally relates to a method for manufacturing a circuit board, and more particularly to a method for manufacturing a circuit board having an embedded component therein, the method decreasing the thickness of the electrode of the embedded component by a thickness decreasing process.
2. Description of the Related Art
A conventional circuit board is mainly constituted by repeatedly laminating a patterned circuit layer and a dielectric layer to each other. The patterned circuit layers are formed by photolithography and etching processes, and the dielectric layer is disposed between two of the patterned circuit layers for isolating the two neighbor circuit layers from each other. In addition, the two neighbor circuit layers are electrically connected to each other by a plating through hole (PTH) or a conductive via passing through the dielectric layer. Finally, various electronic elements (e.g. active components or passive component) are disposed on the surface of the circuit board, and achieve an objective of electrical signal propagation by means of a circuit design of inner traces.
Generally, the electronic elements are soldered on the surface of the circuit board of the conventional electronic product. However, the market demand is that an electronic product is light, thin, short, small and conveniently carried. Thus, an electronic element is designed to an embedded component embedded in the circuit board of the current electronic product so as to increase a wiring area on the surface of the circuit board and to achieve the objective of miniaturization of the electronic product.
FIGS. 1 to 5 depict that a conventional method for manufacturing a circuit board having an embedded component therein. Referring to FIG. 1, a core layer 110 is firstly provided, wherein the core layer 110 includes a first dielectric layer 112, a first patterned circuit layer 114 and a second patterned circuit layer 116. The first patterned circuit layer 114 and the second patterned circuit layer 116 are located on the upper surface 112a and the lower surface 112b of the first dielectric layer 112 respectively.
Referring to FIG. 2, a through hole H1 is formed in the core layer 110, and an embedded component E is disposed in the through hole H1, wherein the embedded component E has two sides 112c, 112d and two electrodes E1, the two sides 112c, 112d face the first dielectric layer 112, and the two electrodes E1 are located on the two sides 112c, 112d of the embedded component E respectively.
Referring to FIG. 3, first and second stacking layers 120, 130 are disposed on the first and second patterned circuit layers 114, 116 respectively, wherein the first stacking layer 120 includes a first metallic layer 122 and a second dielectric layer 124, the second stacking layer 130 includes a second metallic layer 132 and a third dielectric layer 134, and the second and third dielectric layers 124, 134 face the first and second patterned circuit layers 114, 116 respectively.
Referring to FIG. 4, the first stacking layers 120, the core layer 110 and the second stacking layers 130 are laminated, and at least one conductive via H2 and a plurality of conductive vias V are formed. The conductive via H2 passes through the first stacking layer 120, the core layer 110 and the second stacking layer 130, whereby the first metallic layer 122 and the second dielectric layer 124 can be electrically connected to each other by the conductive via H2. In addition, the two electrodes E1 of the embedded component E can be electrically connected to the first metallic layer 122 and the second metallic layer 132 respectively by the conductive vias V.
Referring to FIG. 5, the first metallic layer 122 and the second metallic layer 132 are patterned so as to respectively form a first surface circuit 122′ and a second surface circuit 132′. The first surface circuit 122′ and the second surface circuit 132′ are electrically connected to each other by the conductive via H2, and the two electrodes E1 of the embedded component E are electrically connected to the first surface circuit 122′ and the second surface circuit 132′ by the conductive vias V so as to finish the conventional method for manufacturing a circuit board having an embedded component therein.
However, the embedded component E in the conventional method for manufacturing a circuit board must be electrically connected to the first surface circuit 122′ and the second surface circuit 132′ by the conductive vias V such that wiring areas on the first patterned circuit layer 114 and the second patterned circuit layer 116 are decreased, and further wiring densities on the first patterned circuit layer 114 and the second patterned circuit layer 116 are decreased. In addition, the embedded component E must be electrically connected to the first surface circuit 122′ and the second surface circuit 132′ by the conductive vias V such that the thickness of the whole circuit board can be increased. Thus, the conventional circuit board can not meet the requirements of light, thin, short and small product.
Taiwan Patent Application Number 095104698 is filed on Feb. 13, 2006 (the application date). The applicant of this Taiwan patent application is same as that of the present application: Advanced Semiconductor Engineering, Inc. This patent application discloses a conventional method for manufacturing a board having an embedded component therein including the following steps as follows. Firstly, a core layer 210 is provided, wherein the core layer 210 includes a dielectric layer 212, a first patterned circuit layer 214 and a second patterned circuit layer 216. The first patterned circuit layer 214 and the second patterned circuit layer 216 are located on the upper surface 212a and the lower surface 212b of the dielectric layer 212. A through hole H3 is formed in the core layer 210. The core layer 210 is disposed on a supporting plate (nor shown), and an embedded component E′ is disposed in the through hole H3, wherein the embedded component E has two sides 212c, 212d and at least one electrode E1′, the two sides 212c, 212d face the dielectric layer 212, and the electrode E1′ is located on the sides 212c, 212d of the embedded component E′. The embedded component E′ is mounted in the through hole H3 by an adhesive in an encapsulating process. The supporting plate is removed. Finally, the electrode E1′ of the embedded component E′ is electrically connected to the second patterned circuit layer 216 by forming a metallic layer L on the lower surface 212b of the dielectric layer 212, shown in FIG. 6. It is not necessary that the embedded component E′ of this Taiwan patent application is electrically connected to a surface circuit by a convention conductive via, whereby wiring areas on the first patterned circuit layer 214 and the second patterned circuit layer 216 can be increased, and further wiring densities on the first patterned circuit layer 214 and the second patterned circuit layer 216 can be increased. In addition, it is not necessary that the embedded component E′ is electrically connected to the surface circuit by the convention conductive via, whereby the thickness of the whole circuit board cannot be increased. Thus, the circuit board can meet the requirements of light, thin, short and small product.
However, this Taiwan patent application only discloses that the electrode E1′ of the embedded component E′ is located on the sides 212c, 212d (the sides 212c, 212d face the dielectric layer 212) of the embedded component E′, but fails to disclose that the electrode E1′ of the embedded component E′ is located on an upper surface 212a or a lower surface 212b of the embedded component E′ (the upper surface 212a and the lower surface 212b does not face the dielectric layer 212).
U.S. Pat. No. 7,033,862 B2, entitled “Method of Embedding Semiconductor Element in Carrier and Embedded Structure Thereof”, discloses a conventional method for embedding a semiconductor element in carrier including the following steps as follows. Firstly, a carrier 310 having a through hole 301 is provided, and an auxiliary material 311 is attached to a lower side of the carrier 310. A semiconductor element 312 is placed in the through hole 301 of the carrier 310. Then, a medium material 313 and a glue 314 are applied in order in the through hole 301 to firmly position the semiconductor element 312 in the hole 301 of the carrier 310 by the glue 314. Finally, the auxiliary material 311 and the medium material 313 are removed so as to form a structure with the semiconductor element 312 being embedded in the carrier 310, shown in FIG. 7, thereby eliminating the drawbacks encountered in packing the semiconductor element in the prior art. However, U.S. Pat. No. 7,033,862 B2 fails to disclose that the electrode 315 of the semiconductor element 312 (i.e. embedded component) is electrically connected to a circuit layer of a circuit board.
Accordingly, there exists a need for a method for manufacturing a circuit board having an embedded component therein, the method being capable of solving the above-mentioned problems.